Overview

LabVIEW real time provides a rapid prototyping platform for embedded control systems. Using the real-time features on a cRIO can easily achieve 1ms loop times (as a minimum) which can be further enhanced by using the cRIO FPGA module. This post focuses on common pitfalls in using the cRIO RT loop.

Can we robustly achieve 1ms loop times?

The timed loop structure in LabVIEW real time on a standard cRIO (for example cRIO 9035 or cRIO 9038) will achieve 1ms loop timing, even at relatively heavy CPU load. To actually achieve this, ensure that the scan engine update rate is set to 1ms as shown below. Otherwise, the timed loop might perform at 1ms, but the shared variable within this loop will not actually be updated at this rate. The scan engine setting can be set to less than 1ms, but this can lead to jitter on the data. A 1ms loop time ensures robust timed loop and C-series timings.

Can we accidentally break the real-time behaviour?

Yes we can! We should avoid accessing front panel functionality as much as possible. Simple indicators will work fine (even in a 1ms RT loop), but accessing for example property nodes entirely kills the RT performance. The first example below accesses the color property node of a bar indicator. This increases loop timings to well over 1ms (around 10 ms on a cRIO 9038).

To resolve this, introduce shared variables wherever possible. These shared variables should have a single element RT FIFO to ensure that determinist loop and non-deterministic loops are de-coupled.

The de-coupling is then achieved by introducing a non-deterministic while loop. The while loop (shown with 100ms update rate) updates the graphics. The time loop looks after any deterministic RT functionality. The single-element FIFO shared variable de-coupled these two loops. This now ensures that the time loop completes deterministically within 1ms.

What next?

We aim to continuously extend our technical blogs, and upcoming blogs will feature more LabVIEW RT performance tips and tricks, as well as diving into FPGA performance. If you have suggestions for future blogs or any questions just email us.